library verilog;
use verilog.vl_types.all;
entity FREQUENCY_DIVIDER is
    generic(
        sys_clk_fre_value: integer := 50000000;
        div_clk_fre_value: integer := 100000;
        div_count_value : vl_notype
    );
    port(
        i_sys_clk       : in     vl_logic;
        i_sys_rst       : in     vl_logic;
        o_div_clk       : out    vl_logic
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of sys_clk_fre_value : constant is 1;
    attribute mti_svvh_generic_type of div_clk_fre_value : constant is 1;
    attribute mti_svvh_generic_type of div_count_value : constant is 3;
end FREQUENCY_DIVIDER;
